In the flash memory and stored data erasing method thereof disclosed in Japanese Unexamined Patent Publication No. 2003-36680, when erasing a plurality of sectors, the addresses of the sectors to be erased are input so that their associated sector selection information TSAi goes to a high level and is input to a selector latch circuit 240 shown in FIG. 10. In the selector latch circuit 240, a selector latch pulse LACLK goes to a high level as one shot pulse, thereby latching the sector selection information TSAi in a latch circuit composed of inverter circuits 250, 260.
The latched sector selection information TSAi is input to an exclusive OR circuit 270 as erase sector information LASAi. Sector selection information ISAi generated in an internal address generation circuit is also input to the exclusive OR circuit 270. During erasing operation, a match comparison between the erase sector information LASAi and the sector selection information ISAi is performed in the exclusive OR circuit 270. Whenever the sector selection information ISAi sequentially generated by the internal address generation circuit coincides with the erase sector information LASAi latched as a sector to be erased, the erasing operation is performed.
According to Japanese Unexamined Patent Publication No. 2003-36680, each piece of erase sector information LASAi, which is 1 bit data used for identifying a sector to be selected, is latched by the latch circuit composed of the inverter circuits 250, 260. The inverter circuits 250, 260 that constitute the latch circuit are logic gates used for performing normal logic operation and are configured to have satisfactory load driving ability. Therefore, they disadvantageously occupy large area, compared to memory cells etc. capable of storing 1 bit data.
Under present circumstances, the number of sectors provided in a nonvolatile storage is increasing with the increasing capacity of nonvolatile storages and therefore, the number of bits of erase sector information LASAi that informs whether each sector is to be erased also increases. This brings about the problem that the latch circuit for storing the erase sector information LASAi unavoidably increases in circuit scale, occupying larger area.